The present invention relates to a semiconductor integrated circuit device.
In semiconductor integrated circuits, particularly MOS (metal oxide semiconductor) integrated circuits, the MOS transistors are more and more microminiatureized. With this tendency, the depth of the source and drain regions are shallowed or the length of the gate region i.e. the channel length or the thickness of the gate insulation film is reduced. Although the size of the MOS transistor and the thickness of the gate insulation film are more reduced, a power source voltage still employs a high voltage, for example, +5 V. It is for this reason that other integrated circuits, for example, TTL (transistor transistor logic), are fabricated into an overall system, and it is undesirable to use different power sources for the respective integrated circuits from a practical view point. Because of the high power source voltage, when impact ionization takes place in the vicinity of the drain region, electrons are injected into the gate insulation film, resulting in a variation of the threshold voltage. The variation of the threshold voltage causes various problems. A measure conventionally taken for raising the punch-through voltage is to raise an impurity concentration in the channel region by the iron implantation process.
The measure taken, however, not only complicates the manufacturing process of the semiconductor device but also needs much labors.
A conventional memory device, such as ROM, in which each memory cell is constituted of a single MOS transistor, is illustrated in FIG. 1. In the figure, memory cells M (1, 1), M (1, 2), . . . are disposed at cross points of row lines, R1, R2, . . . and column lines S1, S2, . . . , which are arranged orthogonal to the row lines. In reading data from the memory array thus constructed, a row line decoder 41 selects one of the row lines R1, R2, . . . and a column line decoder (not shown) selects one of the column lines S1, S2, . . . , so that a memory cell disposed at the cross point of the selected row line and the selected column line is specified to provide data stored therein. When the selected memory cell is connected at the drain to the column line, such as M (1, 1) and M (1, 3), the charge on the column line is discharged through the transistor and its potential is at "0" level. On the other hand, when the drain of the memory cell transistor is opened, the column line is charged by the power supplied from the power source through a load transistor (not shown) connected to the column line to have a potential of "1" level. In this manner, the data of "0" or "1" is read out from the memory cell.
In the above-mentioned ROM, since the single memory cell is constituted by a single transistor, it is possible to microminiaturize the memory cell transistor and hence to reduce the chip size. When the memory cell is made small, the channel length is also shortened correspondingly. The resultant short channel effect reduces the threshold value to pull the threshold voltage of the transistor to the negative value. The result is that the memory cells not selected are conductive. Under this condition, at the time of selecting the column line, the non-selected memory cells are turned on, so that the potential on the row line does not rise to fail to provide a "1" level signal. When the drain voltage is applied to the memory cell transistor, the height of the potential barrier between the source and the drain is limited to a low value, so that a current which is not very dependent on the gate voltage flows through the source-drain path. This current is a so-called space charge limiting current. The current punches through the source and drain. Under this condition, the charge potential on the column line does not rise. For this reason, there is a limit in microminiaturizing the memory cell and thus in improving an integration density of the ROM.
The non-volatile memory device using the MOSFET with a floating gate as the memory cell has the same problem of microminiaturizing the memory cells and the memory chips for increasing memory capacity. The reduction of the memory size indicates the shortening of the channel length. This leads to a problem of excessive reduction of the threshold voltage due to the short channel effect or the punch-through due to the drain voltage. When a high voltage is applied to the drain of the memory cell in a write mode of the memory device, the leakage current flows into the non-selected memory cell of which the gate voltage is 0 V. The leakage current is not negligible when the memory capacity of the memory is large, since the number of the drains of the memory cells connected to the same row line is large in such a case. This brings about a disadvantage that the data write characteristic is deteriorated since the drain voltage is dropped in a data write mode.
An example of the memory device developed for improving this problem is shown in FIG. 2. This memory device is designed on the basis of the concept that a fixed potential is applied from a voltage signal supply circuit 101 to the source of each memory cell T of the memory cell array in a data write mode, thereby to prevent the reduction of the punch-through voltage and the deterioration of the write characteristic in a write mode. Incidentally, R1, R2 and R3 are row lines and S1, S2 and S3 are column lines. As the voltage signal supply circuit 101, an arrangement as shown in FIG. 3 or FIG. 4 may be considered. The circuit shown in FIG. 3 is constituted of a resistor element (which may be a MOS-FET) which is connected to the ground at one end and at the other end to a source connection point S of the memory cell T. In a write mode, a current of 1 mA to 2 mA flows into one memory cell and accordingly the source potential may be raised by the voltage drop across the resistor element R. On the other hand, in a data read mode, a current of about 100 .mu.A or so flows into one memory cell. At this time, the source potential rises only a little.
In the circuit shown in FIG. 4, transistors T1 to T4 are of the enhancement type, transistors T5 and T6 are of the depletion type, and a transistor T0 has substantially the same size and characteristic as those of the memory cell T. Also in the circuit, Vc is normally a power source, V.sub.p is a power source for supplying a high voltage in a data write mode, V.sub.A a control potential amount equal to the potential on the non-selected row line in a memory array, R/W a control signal which is "1" in a read mode and "0" in a write mode. When a high voltage power V.sub.p is applied in a write mode, the drain of the transistor T0 is almost equal to that on the selected row line in the memory array, so that the source potential of the transistor T0 gradually rises due to the punch-through up to a value to stop the punch-through. The resistance of the transistor T5 is sufficiently large in preparation for the case when the source of the transistor T0 is at an abnormal potential due to noise or the like to discharge its high potential.
The threshold voltage of the transistor T2 is set at about 0 V, and its gate is at a voltage at which the punch-through of the transistor T0 equivalent to the memory cell stops. For this reason, the transistor T2 is cut off when the potential Vs at the source connection point S in the memory cell array reaches the potential at the gate of the transistor T2. The transistor T3 is connected to the power source Vc through the transistor T6. Accordingly, the gate potential rises and the transistor T3 turns on. As a result, the potential Vs at the source connection point S is set at a value to stop the punch-through of the transistor T0 equivalent to the memory cell, that is, to stop the punch-through of the non-selected memory cell of those memory cells. In the data write mode, a signal R/W is "0" and the transistor T4 is off. On the other hand, in the data write mode, the R/W signal is "1" and hence the transistor T4 is on, so that the source connection point S is kept at substantially 0 V.
With the further reduction of the memory size resulting from the large capacity of the memory, the channel length of the memory cell is even shorter. As a result of the shorter channel, the threshold voltage abnormally drops to a negative value. In this case, the leakage current in the read mode is not negligible in the memory cells. In this respect, there is a need for developing a means which sets the potential Vs at the source connection point S at a value higher than the gate potential of the non-selected memory cell not only in the write mode but also in the read mode.
The semiconductor integrated circuit is provided with means to stop the power supply to a circuit block in the integrated circuit when it is not used, for reducing the consumption of the power source current. For example, the semiconductor memory has a power down mode in which the memory chips not selected are made inoperative for the power saving.
In the integrated circuit with the power down function, MOS transistors T11 to T13 are connectd in series across the power source (between Vc and ground), as shown in FIG. 5. The load MOS transistor (referred to as a load transistor) T12 is an n-channel depletion MOS transistor and the drive MOS transistor (referred to as a drive transistor) T13 is an n-channel MOS transistor used as an inverter. The gate of the load transistor T12 and the drain of the drive transistor T13 are connected to each other to provide an output terminal A0.
An input signal ai is applied to the gate of the drive transistor T13. The power source Vc is supplied to the load transistor T12, through the MOS transistor T11 of the n-channel depletion type. The power supply control MOS transistor (referred to as a control transistor) T11 is gate-controlled by a power down mode signal PD. The power down mode signal PD is "0" when the power down is carried out by using the inverted signal of the signal PD, that is, when the power saving is made by rendering the inverter inoperative, and is "1" when the power down mode is removed.
Further, a control MOS transistor T14 is provided between the output terminal A0 and ground, in parallel with the drive transistor T13. The control transistor T14 is an n-channel enhancement MOS transistor, for example, which is gate-controlled by the power down mode signal PD. The power down mode signal PD is "1" in the power down mode and "0" when the power down mode is removed.
Further, a circuit comprised of MOS transistors T15 to T18 is provided, like the circuit comprised of MOS transistors T11 to T14. The MOS transistor T17 is gate-controlled by a signal from the output terminal A0 of the inverter. The MOS transistors T15 and T18 are gate-controlled by the signals PD and PD, as in the above case.
In the integrated circuit, when the control transistor T11 is conductive, the power source Vc is supplied to the load transistor T12, and the control transistor T14 is in a cut-off state, the inverted signal of the input signal ai appears at the output terminal A0. At this time, power down mode signals PD and PD are "1" and "0", respectively. For setting the integrated circuit in the power down mode by rendering the circuit inoperative, the signals PD and PD are "0" and "1", respectively, so that the control transistor T11 is substantially in the cut-off state, while the control transistor T14 is in an on-state. In this way, the supply of the power voltage Vc to the load transistor T12 is stopped and a signal appearing at the output terminal A0 flows to ground through the control transistor T14.
To completely stop the power voltage Vc supply to the load transistor T12 at this time, i.e. in the power down mode, the threshold voltage Vth11 of the control transistor T11 must be above 0 V or more. In this case, when the power down is removed, that is, when the integrated circuit operates, a signal at "1" level appearing at the output terminal A0 of the inverter made up of the transistors T12 and T13 rises up to only a level of "Vc-Vth11", which is below the power source voltage Vc. Therefore, the power source margin of the integrated circuit is reduced.
On the other hand, in order to raise the output signal level to the substantial power source voltage Vc during operation of the integrated circuit, when the threshold voltage Vth11 of the control transistor T11 (of the depletion type) is set at a value of less than 0 V, the control transistor T11 is not cut off, if the power down signal PD is "0". Also, the current feed to the load transistor T12 continues, so that there is little power saving. When the threshold voltage Vth11 of the control transistor T12 is made negative, the reduction of the power source margin can be avoided. In this case, however, the current (flowing through the source-drain path) in the power down mode is sensitive to the threshold voltage Vth11 or the channel length of the control transistor T11, so that the current consumption varies greatly in the power down mode. In this respect, great care must be taken in setting the threshold voltage Vth11 or the channel length of the control transistor T11 when the transistor T11 is manufactured.
In addition to the power saving circuit in the integrated circuit, there is proposed another circuit, as shown in FIG. 6, in which a control MOS transistor is provided between drive transistors T13 and T17 making up an inverter and ground, and the control transistor is gate-controlled by the power down mode signal PD. In such an integrated circuit, the signal PD is "0" in the power down mode, and the control transistor T20 is cut off, to save the power consumption. In this system, however, all the circuit points rise to the "1" level in the power down mode and the charges thereat are discharged when the power down mode is removed. The substrate potential is pulled down in the negative direction by the capacitive coupling of the substrate of the integrated circuit with the circuit points, so that the substrate potential varies to adversely influence the operation of the integrated circuit. At the time of releasing the power down mode, time must be taken for the drain voltage of the transistor T20 to change from "1" to "0" against the change of the signal PD from "0" to "1" when the power down mode is removed. In this case, the presence of the mirror feedback capacitance delays the releasing of the power down. In the system shown in FIG. 5, it is satisfactory that the control transistors T11 and T14 are connected every other inverter (MOS transistors T12 and T13, and T16 and T17). In the system shown in FIG. 6, the control transistors T11 and T14 must be connected to all of the inverters since the outputs of the inverters are at "1" level. In order to keep the drain potential of the control transistor T20 at about ground potential so as to ensure the normal operation of each inverter, the drive ability of the transistor T20 must be great, with the result that the chip area of the integrated circuit becomes large.